White Paper Overview

Every design company constantly evaluates their design flow to identify opportunities for faster design development, implementation and verification. Time-to-market is a critical commodity in the electronics industry. Replacing inefficient, imprecise processes with smarter, more accurate and faster functionality can improve both the bottom line and product quality.

Using a P&R tool’s built-in fill function to place filler cells during implementation is not only time-consuming, but can create layouts that do not comply with design requirements. Removing and replacing these non-compliant filler cells during verification costs even more time and resources.

In this white paper by Siemens, learn how the use of the Calibre YieldEnhancer PVReady flow to insert filler, DCAPs and ECO cells during P&R is a prime example of designers using existing technology in new ways to eliminate time-consuming tasks without sacrificing design quality. The proven, analysis-based layout modifications performed by the Calibre YieldEnhancer tool ensures correct-by-construction filler cell insertion in less time, while using standard industry interfaces that seamlessly integrate with both the P&R and physical verification tools. In addition, because filler cells must be replaced throughout the design process, the runtime reductions are additive, which can significantly reduce time to tapeout. Over the span of a design flow, reducing the number of DRC errors and enabling designers to begin physical verification earlier results in faster tapeouts and higher quality designs.