White Paper

Integrating multiple dies and substrates into a single package continues to be a major focus of the semiconductors industry. Compared to the traditional transistor scaling approach, advanced packaging promises improved form factor, cost, performance, and functionality as well. 2.5D-IC technologies are used to connect multiple dies side by side using an interposer which can be silicon-based or organic. On the other hand, in fan-out wafer level packaging technologies, multiple dies are connected through the package routing.

In this white paper by Siemens, learn how a system level designer can utilize aggregated data to automatically generate a complete assembly verification run set (i.e., the full assembly description and comprehensive assembly checks). This assembly verification approach using Xpedition Substrate Integrator and Calibre 3DSTACK is a “designer-centric” approach, as it is agnostic to the different die technology nodes and substrate manufacturers.