White Paper Overview

The increasing complexity in large System on Chip (SoC) designs presents challenges to all IC design disciplines, including design-for-test (DFT). To alleviate some of those challenges, hierarchical DFT is used as a divide and conquer approach, where all DFT implementation (including pattern generation and verification) is done at the core level rather than the chip level. However, hierarchical DFT by itself is no longer enough. DFT managers have to make difficult, and sometimes costly, trade-offs between test implementation effort and manufacturing test cost.

This white paper describes the basic components of the Tessent Streaming Scan Network (SSN), a technology designed to decouple core level and chip level DFT requirements. With SSN, DFT engineers can - for the first time - implement DFT using a true, effective bottom-up flow, not having to make trade-offs between implementation effort and manufacturing test cost.