White Paper Overview

RF circuits are very sensitive to parasitic elements and layout-dependent effects, so both pre-and post-layout simulations are essential to ensuring a robust circuit that performs reliably over a broad range of operating conditions. But simulations are time-consuming and resource-intensive.

Circuit designers must work closely with the mask layout engineers to ensure that circuits are laid out so as to minimize the impact of parasitics on the circuit operation. In particular, special consideration must be given to the insertion of fill patterns in the layout. While fill only affects capacitance at lower frequencies, it can also significantly alter resistance and inductance when higher frequencies are used.

This white paper looks closely at the types of checking that can be used to find and eliminate impacts on reliability and performance. It also covers how advanced electronic design automation (EDA) tools and techniques are helping designers ensure accurate, fast, automated verification and design for manufacturing optimization of RF ICs.